1. Field of the Invention
The present invention relates to semiconductor devices and control methods of the semiconductor devices, and more particularly, to a semiconductor device having sector protection information and a control method of the semiconductor device.
2. Description of the Related Art
A flash memory, which is a non-volatile semiconductor memory, respectively performs operations in response to control commands applied from the outside such as read, program, and erase. In particular, an erase command includes a chip erase that erases all the sectors in a memory region and a sector erase that erases a designated sector. The memory region is composed of multiple sectors, and each of the sectors includes multiple memory cells. The flash memory is the non-volatile memory, and stores contents that have to be retained for a long period such as programs and control data in a system.
Accordingly, the flash memory includes a protect memory that stores protection information so as not to erase the aforementioned contents mistakenly. A memory corresponding to each sector stores the protection information and unprotection information. The protection information prohibits erasing of the sector. The unprotection information allows erasing of the sector. Before one sector is erased based on the erase command, the protection information of the protect memory corresponding to the sector is checked. Only the sector of an unprotection status is erased.
FIG. 1 is a diagram illustrating an erase operation in a conventional flash memory. A conventional flash memory 701 includes a memory cell array 702, a WP (write protect) cell array 703, latch circuits L000 through L511. The memory cell array 702 includes a memory cell in which the data is stored, and is divided into multiple sectors S000 through S511. Here, an example will be given of the memory cells divided into 512 sectors. The WP sell array 703 includes multiple non-volatile memory cells that store the protection information corresponding to each of the above-mentioned sectors. The protection information shows protect or unprotect of the sector. The latch circuits L000 through L511 are provided to be equal in number to the sectors. For example, the flash memory having 512 sectors therein includes 512 latch circuits. The erase operation shown in FIG. 1 is performed by a control circuit (not shown).
The WP cell array 703 is read to retain the protection information in the latch circuits L000 through L511, making use of a read time at the time of power-on. If the protection information of the latch circuit L511 has the unprotection status when a user enters and performs the chip erase and the sector thereof is not to be erased, the control circuit decrements a sector address counter according to a decrement signal, decrements a sector address, and shifts to the next sector for erase operation.
When the control circuit detects that the protection information of the latch circuit has the protection status, the control circuit does not perform erasing in the sector, decrements a sector address counter according to a decrement signal, decrements a sector address, and shifts to the next sector for erase operation. In the next sector, the control circuit checks the protection information. If the protection information shows the unprotection status, the erase operation is performed. If the protection information shows the protection status, the erase operation is skipped. If the protection information of the latch circuit L256 shows the unprotection status, the control circuit applies an erase stress to the selected sector S256 and the erasing is performed.
After the erasing is completed, the control circuit supplies the decrement signal to decrement the sector address counter. Also in the sector S000, when the control circuit detects that the protection information of the latch circuit L000 shows the protection status, the control circuit completes the procedure without erasing the sector S000.
FIG. 2 is a timing chart at the time of powering on a power VCC in the conventional flash memory. This example shows an input signal for reading at the time of power-on. A signal VCCOK is an internal signal and becomes High, when the power VCC reaches a given level. After the power VCC is powered on, a reset signal RST is changed from High to Low. The period of 1 ms for setting the reset signal RST to High is set to the read time of the protection information from the WP cell array 703. Therefore, the protection information of the WP cell array 703 has to be read into the 512 latch circuits L000 through L511 within 1 ms.
However, the conventional flash memory 701 has a problem in that the read time has to be created at the time of power-on and the latch circuit equal in number to the sectors is required. This is because, at the read time of power-on, the WP cell array 703 is read, the protection information is stored in the latch circuits L000 through L511, and the sector address is sequenced to check the protection information and erase the sector.